1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device wherein via holes are formed.
2. Background Art
In a device using a compound semiconductor, the heat dissipation properties of the device must be improved to operate transistors at high frequency. Furthermore, the circuit must be securely grounded.
In Japanese Unexamined Patent Publication No. 7-193214, a wiring structure, wherein via holes that penetrate through the substrate are formed to connect the top side of the substrate to the back side thereof, is described.
As a compound semiconductor substrate, an SiC substrate, which excels in heat dissipation properties, is frequently used. When via holes are formed in the SiC substrate, Ni, which has a high etching selection ratio to the SiC substrate, is used as an etching mask.
Here, when the via holes are formed, etching for the thickness of the substrate (about 100 μm) is performed so as to penetrate through the substrate. Therefore, an Ni film having a thickness of about 3 to 4 μm must be previously formed on the SiC substrate. When such a thick Ni film is formed, an electrolytic plating method or a non-electrolytic plating method is used to enhance throughput.
In the above-described plating methods, when a non-electrolytic plating method is used, a Pd film is formed on the SiC substrate, and Ni plating is performed using the Pd film as a catalyst. At this time, if the Pd film is formed directly on the SiC substrate, adhesiveness between the SiC substrate and the Pd film is weakened. Therefore, when an Ni film is formed by plating, the Pd film may peel off due to the stress of the Ni film. Then, a problem that favorable via holes cannot be formed arises.